This invention relates to an integrated current-mirror arrangement comprising a first and a second transistor whose bases are interconnected and coupled to the collector of the first transistor.
Current-mirror arrangements are known per se in a wide variety and therefore require no further explanation. If a current-mirror arrangement is to be realized by means of vertical transistors, the problem arises that in vertical transistors the parasitic capacitances formed between the collector region and the intermediate layer separating the collector region from the substrate adversely affect the correction operation of the arrangement. Said intermediate layer, which is of a conductivity type opposite to that of the collector regions, should be at such a voltage that the junction between the collector region and said intermediate layer and the junction between the substrate and the intermediate layer cannot be turned on. For this purpose the intermediate layer is normally connected to a positive power-supply terminal or to the emitter of the relevant vertical transistor. In the case of a current-mirror arrangement this would result in the parasitic capacitance between the collector region and the intermediate layer being connected in parallel with the main current path of the transistor, which gives rise to an undesirable high-frequency pole in the transfer function between the input current and the output current of the current-mirror arrangement. Moreover, it results in an undesirable capacitive connection for interference signals from the power-supply line to the output current terminal.